Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever increasing variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Generally, the principle underlying the storage of data in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher its coercivity.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory are commonly referred to as spin valve memory cells (SVM). FIGS. 1 and 2 provide a perspective view of a typical prior art magnetic memory cell.
As shown in prior art FIGS. 1 and 2, a magnetic spin valve memory (SVM) cell 101 generally includes a data layer 103 which may alternatively be called a storage layer or bit layer, a reference layer 105, and an intermediate layer 107 between the data layer 103 and the reference layer 105. The data layer 103, the reference layer 105, and the intermediate layer 107 can be made from one or more layers of material. Electrical current and magnetic fields may be provided to the SVM cell 101 by an electrically conductive row conductor 109 and an electrically conductive column conductor 111. It is understood and appreciated that as used herein, the terms row and column conductor have been selected for ease of discussion. Under appropriate circumstances these labels may be reversed and or otherwise substituted for such titles as word line and bit line.
The data layer 103 is usually a layer of magnetic material that stores a data bit as an orientation of magnetization M1 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M1 of the data layer 103 representing the logic state can be rotated (switched) from a first orientation 117, representing a logic state of “0”, to a second orientation 119, representing a logic state of “1”, and/or vice versa.
The reference layer 105 is usually a layer of magnetic material in which an orientation of magnetization M2 is “pinned”, as in fixed, in a predetermined direction, or pinned orientation 121. The direction is predetermined and established by conventional microelectronic processing steps employed in the fabrication of the magnetic memory cell 101.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization M1 in the data layer 103 and M2 of the reference layer 105—first orientation 117 to pinned orientation 121, as shown in FIG. 1, or second orientation 119 to pinned orientation 121, as shown in FIG. 2. For example, when an electrical potential bias is applied across the data layer 103 and the reference layer 105 in the SVM cell 101, electrons migrate between the data layer 103 and the reference layer 105 through the intermediate layer 107. The intermediate layer 107 is typically a thin dielectric layer, which is commonly referred to as a tunnel barrier layer. The phenomenon that causes the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
The logic state may be determined by measuring the resistance of the SVM cell 101. For example, if the second orientation 119 of the magnetization M1 in the data layer 103 is parallel to the pinned orientation 121 of magnetization in the reference layer 105, the SVM cell 101 will be in a state of low resistance, R, see FIG. 2.
If the first orientation 117 of the magnetization M1 in the data layer 103 is anti-parallel (opposite) to the pinned orientation 121 of magnetization in the reference layer 105, the SVM cell 101 will be in a state of high resistance, R+ΔR, see FIG. 1. The orientation of M1 and, therefore, the logic state of the SVM cell 101, may be read by sensing the resistance of the SVM cell 101.
The resistance may be sensed by applying a voltage to a selected SVM cell 101 and measuring a sense current that flows through the SVM cell 101. Ideally, the resistance is proportional to the sense current.
The single SVM cell 101 shown in FIGS. 1 and 2 is typically combined with other substantially identical SVM cells. In a typical MRAM device, the SVM cells are arranged in a cross-point array. Parallel conductive columns (e.g., column 1, 2, 3 . . . ), also referred to as word lines, cross parallel conductive rows (e.g., row A, B, C . . . ), also referred to as bit lines. The traditional principles of column and row arrays dictate that any given row will only cross any given column once.
An SVM cell is placed at each intersecting cross-point between a row and a column. By selecting a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B,3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities.
A typical MRAM cross-point array may easily consist of 1,000 rows and 1,000 columns uniquely addressing 1,000,000 SVM cells. Sensing the resistance state of a given SVM cell in the cross-point array can be unreliable. The cross-point array may be characterized as a resistive cross-point device. All of the resistive elements (the SVM cells) within the array are coupled together through the parallel sets of row and column conductors. The resistance between a selected row and a selected column equals the resistance of the element at that cross point (R) in parallel with a combination of resistances of the unselected resistive elements (2R/1000+R/1000000).
Unselected resistive elements are also prone to permitting the development of sneak path current, ΔV*1000/R. Where R is on the order of 1 mega-ohm and ΔV is 50 milli-volts, there will be 50 pico-amps per sneak path, or 50 nano-amps where there are 1,000 rows. Expanding the cross-point array to 10,000×10,000 the combined sneak path current may total 500 nano-amps.
The efficiency of a sense amplifier detecting changes in sense currents on the order of 20 to 50 nano-amps when the selected memory element is changed from R to R+ΔR is reduced in the presence of large sneak path currents. Sense amplifiers can be made to operate when the ratio of sense current to sneak path current is as undesirable as 1 over 10 (1/10). If the sneak path current is increased as in the example, from 50 nano-amps to 500 nano-amps when sensing a signal current of 20 nano-amps, the reliability of the sense amplifier will be reduced.
Understanding the propensity for sneak current to occur in the memory array, design parameters should be accordingly accommodating. The effective size of a typical resistive memory cross-point array is therefore limited to about 1,000×1,000, since a larger array may permit a combined sneak path current that overshadows the detection of a change within a single given memory cell. More simply stated, as the size of the array increases, the ability to measure and detect the change of resistance within a single cell generally decreases.
Adding switches such as series select transistors to each resistive element to aid in their isolation has proven costly in the past, both in terms of space within the array and the complexity of manufacturing. In addition, a series select transistor is a three terminal device while a resistive element such as an SVM cell is a two terminal device.
Hence, there is a need for an ultra-high density resistor device, such as a magnetic memory device, which overcomes one or more of the drawbacks identified above.